stnolting/neorv32: :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. [https://github.com/stnolting/neorv32] - 2024-03-31 07:29:41 - public:speqz riscv - 1 | id:1490820 -
RISC-V 指令集架構介紹 - Integer Calling convention | Jim's Dev Blog [https://tclin914.github.io/77838749/] - 2023-12-01 09:30:33 - public:speqz instruction, riscv - 2 | id:1485416 -
riscv-collab/riscv-gnu-toolchain: GNU toolchain for RISC-V, including GCC [https://github.com/riscv-collab/riscv-gnu-toolchain] - 2023-11-30 04:08:55 - public:speqz gcc, riscv - 2 | id:1485394 -
syntacore/scr1: SCR1 is a high-quality open-source RISC-V MCU core in Verilog [https://github.com/syntacore/scr1] - 2023-11-30 03:54:06 - public:speqz core, riscv - 2 | id:1485393 -
與妖精共舞：在 RISC-V 架構上使用 GO 語言實作 binutils 工具包 :: 2018 iT 邦幫忙鐵人賽 [https://ithelp.ithome.com.tw/users/20103524/ironman/1348?page=1] - 2020-04-01 23:39:46 - public:speqz gcc, riscv - 2 | id:290995 -
