66786 - UltraScale+/ Zynq UltraScale+ MPSoC SelectIO: Interfacing LVDS signals with 1.2V I/O banks [https://support.xilinx.com/s/article/66786?language=en_US] - 2022-12-30 23:37:06 - public:speqz lvds, voltage, xilinx - 3 | id:1294746 -
